BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:Europe/Stockholm
X-LIC-LOCATION:Europe/Stockholm
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=-1SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=-1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20210916T132456Z
LOCATION:
DTSTART;TZID=Europe/Stockholm:20210706T173000
DTEND;TZID=Europe/Stockholm:20210706T190000
UID:submissions.pasc-conference.org_PASC21_sess182_post144@linklings.com
SUMMARY:P22 - CPU and FPGA Performance Comparison of a Conjugate Gradient 
 Solver Extracted from a Molecular Dynamics Code
DESCRIPTION:Poster\n\nP22 - CPU and FPGA Performance Comparison of a Conju
 gate Gradient Solver Extracted from a Molecular Dynamics Code\n\nProuveur,
  Haefele, Voss\n\nFPGA devices used in the HPC context promise an increase
 d energy efficiency, enhancing the computing systems Flop/W rate. This wor
 k compares an FPGA and a CPU implementation of a conjugate gradient solver
  in terms of both time to solution and energy to solution metrics. The sta
 rting point is MetalWalls, a molecular dynamics code developed at Sorbonne
  University in Pr. M. Salanne's team, capable of computing accurately the 
 charge and discharge cycles of supercapacitors (energy storing devices). I
 n the context of the H2020 EXA2PRO project, a miniapp has been derived fro
 m the F90 pure MPI production code, extracting the core of the electrostat
 ic computation. The FPGA version has been implemented with the Data Flow E
 ngine (DFE) software toolchain developed by Maxeler. Additionally, since F
 PGAs can perform arithmetic operations with any number of bits instead of 
 the "standard" 32 or 64 bits, the miniapp could be further accelerated usi
 ng optimised custom number formats. Thanks to an accuracy analysis based o
 n the CADNA tool and comparisons with quadruple precision runs, this accel
 eration could be achieved without decreasing the computed solution accurac
 y. Finally, the original CPU and the developed FPGA implementations could 
 be compared on Juelich Computing Centre computing systems.
END:VEVENT
END:VCALENDAR