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END:STANDARD
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UID:submissions.pasc-conference.org_PASC21_sess182_post156@linklings.com
SUMMARY:P30 - Improving the Flow: Introducing the Lucent Dataflow Programm
 ing Language for FPGAs
DESCRIPTION:Poster\n\nP30 - Improving the Flow: Introducing the Lucent Dat
 aflow Programming Language for FPGAs\n\nBrown\n\nDataflow architectures, a
 nd specifically Field Programmable Gate Arrays (FPGAs), are demonstrating 
 early but significant potential benefits to HPC. Whilst the community has 
 explored this technology before, recent advances in hardware capability an
 d software environments have made them a far more serious proposition as a
  new HPC computing paradigm. However, whilst it is now possible to write k
 ernels in C/C++ and synthesize these to the underlying circuitry, without 
 completely redesigning algorithms from a dataflow perspective one is typic
 ally stuck with poor performance. The simple reason is that these imperati
 ve languages are based on a Von-Neumann rather than dataflow architecture,
  and instead there is a role for using dataflow programming languages wher
 e the development of these forms of computation for FPGAs is far more natu
 ral. This was an active area of research over 40 years ago, when dataflow 
 languages such as Lucid appeared, but at the time the hardware was lacking
 . We will introduce Lucent, a declarative language for FPGAs whi
 ch is a derivative of Lucid and combines the dataflow computing paradigm w
 ith modern programming language features. The result is a programming lang
 uage which, when mastered, enables fast development of high performance ke
 rnels on FPGAs tuned specifically for these dataflow architectures.
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